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HYB39S16160CT-6/-7 16MBit Synchronous DRAM 1M x 16 MBit Synchronous DRAM for High Speed Graphics Applications
*
High Performance:
-6 fCKmax @ CL=3 tCK3 tAC3 fCKmax @ CL=2 tCK2 tAC2 166 6 5 125 8 6 -7 143 7 5.5 115 9 6 Units MHz ns ns MHz ns ns
* * * * * * * *
full page(optional) for sequencial wrap around Multiple Burst Read with Single Write Operation Automatic Command and Controlled Precharge
Data Mask for Read / Write control Dual Data Mask for byte control ( x16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode 4096 refresh cycles / 64 ms Latency 2 @ 125 MHz Latency 3 @ 166 MHz Random Column Address every CLK ( 1-N Rule) Single 3.3V +/- 0.3V Power Supply LVTTL Interface Plastic Packages: P-TSOPII-50 400mil width ( x16 )
* * * * * *
Fully Synchronous to Positive Clock Edge 0 to 70 C operating temperature Dual Banks controlled by A11 ( Bank Select) Programmable CAS Latency : 2, 3 Programmable Wrap Sequence : Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8
* * * * * *
The HYB39S16160CT-6/-7 are high speed dual bank Synchronous DRAM's based on SIEMENS 0.25m process and organized as 2 banks x 512kbit x 16. These synchronous devices achieve high speed data transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS' advanced 16MBit DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the two memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166 MHz is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3V +/- 0.3V power supply and are available in TSOPII packages. These Synchronous DRAM devices are available with LV-TTL interfaces.
Semiconductor Group
1
10.98
HYB39S16160CT-6/-7 16MBit Synchronous DRAM
Ordering Information
Type Ordering Code Package Description
LVTTL-version:
HYB 39S16160CT-6 HYB 39S16160CT-7 P-TSOPII-50 (400mil) P-TSOPII-50 (400mil) 166MHz 2B x 512k x 16 SDRAM 143MHz 2B x 512k x 16 SDRAM
Pin Description and Pinouts:
CLK CKE CS RAS CAS WE A0-A10 A11 (BS) Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select DQ LDQM, UDQM Vdd Vss Vddq Vssq NC Data Input /Output Data Mask Power (+3.3V) Ground Power for DQ's (+ 3.3V) Ground for DQ's not connected
Pin-Out
Vdd DQ0 DQ1 Vssq DQ2 DQ3 Vddq DQ4 DQ5 Vssq DQ6 DQ7 Vddq LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 Vdd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
Vss DQ15 DQ14 Vssq DQ13 DQ12 Vddq DQ11 DQ10 Vssq DQ9 DQ8 Vddq NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 Vss
Semiconductor Group
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HYB39S16160CT-6/-7 16MBit Synchronous DRAM
Signal Pin Description
Pin
CLK
Type
Input
Signal Polarity
Pulse
Function
Positive The system clock input. All of the SDRAM inputs are sampled on the rising Edge edge of the clock. Active High Active Low Active Low Activates the CLK signal when high and deactivates the CLK signal when low, thereby inititiates either the Power Down mode, Suspend mode or the Self Refresh mode. CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. During a Bank Activate command cycle, A0-A10 defines the row address (RA0-RA10) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address (CA0-CAn) when sampled at the rising clock edge.CAn depends from the SDRAM organisation.
CKE
Input
Level
CS RAS, CAS WE
Input
Pulse
Input
Pulse
A0 A10
1M x 16 SDRAM CAn = CA7 Input Level -- In addition to the column address, A10 is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and A11 defines the bank to be precharged (low=bank A, high=bank B). If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 is used in conjunction with A11 to control which bank(s) to precharge. If A10 is high, both bank A and bank B will be precharged regardless of the state of A11. If A10 is low, then A11 is used to define which bank to precharge.
A11 (BS) DQx
Input Input Output
Level Level
-- --
Selects which bank is to be active. A11 low selects bank A and A11 high selects bank B. Data Input/Output pins operate in the same manner as on conventional DRAMs. The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. Power and ground for the input buffers and the core logic.
LDQM, UDQM
Input
Pulse
Active High
VDD, VSS VDDQ VSSQ
Supply Supply -- --
Power supply and ground for the output buffers to provide improved noise immunity.
Semiconductor Group
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HYB39S16160CT-6/-7 16MBit Synchronous DRAM
Row Decoder Row Decoder Row Decoder Row Decoder
2048 x 512 Memory Bank A 2048 x 256 Memory Bank A 2048 1024 16 512 1024 256
CKE
CKE Buffer Self Refresh Clock
Row Address Counter Bank A Row/Column Select
16
CLK
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 (BS)
CLK Buffer
16 11 Predecode A 3 Sequential Control Bank A
8
8 8 Data Latches Data Latches Data Latches Data Latches 16 8
8
Address Buffers (12)
12
12
11
Mode Register 8 Sequential Control Bank B
CS
CS Buffer 11 Predecode B RAS Buffer Command Decoder
3
16
Data Latches Data Latches 8
RAS
Bank B Row/Column Select
16
Column Decoder and DQ Gate Column Decoder and DQ Gate Sense Amplifiers 256
CAS
CAS Buffer
16
Sense Amplifiers
Row Decoder Row Decoder Row Decoder Row Decoder
WE
WE Buffer
2048 Memory Bank B Memory Bank B 2048 x B Memory Bank256 2048 x 1024 Memory Bank B 2048 x 512 2048 x 1024
UDQM
DQM Buffer
LDQM
DQM Buffer
Block Diagram for HYB39S16160CT (2 banks x 512k x 16 SDRAM)
Semiconductor Group
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Data Input/Output Buffers
Sense Amplifiers Sense Amplifiers Sense Amplifiers Column Decoder and DQ Gate Sense Amplifiers Column Decoder and DQ Gate Column Decoder and DQ Gate Column Decoder and DQ Gate
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
HYB39S16160CT-6/-7 16MBit Synchronous DRAM
Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the most important operation commands.
Operation Standby, Ignore RAS, CAS, WE and Address Row Address Strobe and Activating a Bank Column Address Strobe and Read Command Column Address Strobe and Write Command Precharge Command Burst Stop Command Self Refresh Entry Mode Register Set Command Write Enable/Output Enable Write Inhibit/Output Disable No Operation (NOP)
CS H L L L L L L L X X L
RAS X L H H L H L L X X H
CAS X H L L H H L L X X H
WE X H H L L L H L X X H
(L/U)DQM X X X X X X X X L H X
Mode Register For application flexibility, a CAS latency, a burst length, and a burst sequence can be programmed in the SDRAM mode register. The mode set operation must be done before any activate command after the initial power up. Any content of the mode register can be altered by reexecuting the mode set command. Both banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the following table.
Semiconductor Group
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HYB39S16160CT-6/-7 16MBit Synchronous DRAM
Address Input for Mode Set (Mode Register Operation)
BS A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus (Ax)
Operation Mode
CAS Latency
BT
Burst Length
Mode Register (Mx)
Operation Mode
M11 M10 M9 M8 M7 0 X 0 X 0 1 0 0 0 0 Mode Normal Multiple Burst with Single Write
Burst Type
M3 0 1 Type Sequential Interleave
Burst Length CAS Latency
M6 0 0 0 0 1 1 1 1 M5 0 0 1 1 0 0 1 1 M4 0 1 0 1 0 1 0 1 Latency Reserve 1 2 3 Reserve Reserve Reserve Reserve M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 Length Sequential 1 2 4 8 Reserve Reserve Reserve Full Page*) Interleave 1 2 4 8 Reserve Reserve Reserve Reserve *) optional
Sequential Burst Addressing 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6
Interleave Burst Addressing 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
Semiconductor Group
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HYB39S16160CT-6/-7 16MBit Synchronous DRAM
Read and Write Access Mode When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the word line are fired. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 166 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page, where full page is an optional feature in this device. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is `2', then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5 . Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O organisation and column addressing. Full page burst operation do not self terminate once the burst length has been reached. In other words, unlike burst length of 2, 3 or 8, full page burst continues until it is terminated using another command. Similar to the page mode of conventional DRAM's, burst read or write accesses on any column address are possible once the RAS cycle latches sense amplifiers. The maximum tRAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycles is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies with an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two banks can realize fast serial data access modes among many different pages. Once two banks are activated, column to column interleave operation can be done between two different pages. Refresh Mode SDRAM has two refresh modes, a CAS before RAS (CBR) automatic refresh and a self refresh. All of banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. The chip enters the automatic refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock timing. The mode restores word line after the refresh and no external precharge command is necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. The chip has an on-chip timer and the self refresh mode is available. It enters the mode when RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to any access command.
Semiconductor Group
7
HYB39S16160CT-6/-7 16MBit Synchronous DRAM
DQM Function DQM has two functions for data I/O read write operations. During reads, when it turns to high at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks). Suspend Mode During normal access mode, CKE is held high and CLK is enabled. When CKE is low, it freezes the internal clock and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend Latency tCSL). Power Down In order to reduce standby power consumption, a power down mode is available. Bringing CKE low enters the power down mode and all of receiver circuits are gated. All banks must be precharged before entering this mode. One clock delay is required for mode entry and exit. The Power Down mode does not perform any refresh operation. Auto Precharge Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock before the last data out for CAS latency 2 amd two clocks for CAS latency 3. If CAS10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock delay form the last data-in for CAS latencies of 1 and 2 and two clocks for CAS latencies of 3. This delay is referenced as tDPL . Precharge Command If CA10 is low, the chip needs another way to precharge. In this mode, a separate precharge command is necessary. When RAS and WE are low and CAS is high at a clock timing, it triggers the precharge operation. Two address bits, A10 and A11, are used to define banks as shown in the following list. The precharge command may be applied coincident with the last of burst reads for CAS Latency = 1 and with the second to the last read data for CAS Latencies = 2 & 3. Writes require a time tWR from the last burst data to apply the precharge command.
Bank Selection by Address Bits A10 Bank A Only Bank B Only Both A and B Low Low High A11 Low High Don't Care
Semiconductor Group
8
HYB39S16160CT-6/-7 16MBit Synchronous DRAM
Burst Termination Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. Power Up Procedure All Vdd and Vddq must reach the specified voltage no later than any of input signal voltages. An initial pause of 200 sec is required after power on. All banks have to be precharged and a minimum of 8 auto-refresh cycles are required prior to the mode register set operation.
Semiconductor Group
9
HYB39S16160CT-6/-7 16MBit Synchronous DRAM
Absolute Maximum Ratings Operating temperature range......................................................................................... 0 to + 70 C Storage temperature range..................................................................................... - 55 to + 150 C Input/output voltage .............................................................................. - 0.5 to min(Vcc+0.5, 4.6) V Power supply voltage VDD / VDDQ.......................................................................... - 1.0 to + 4.6 V Power Dissipation............................................. ..........................................................................1 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operation and Characteristics for LV-TTL versions:
TA = 0 to 70 C; VSS = 0 V; VDD,VDDQ = 3.3 V 0.3 V
Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 2.0 mA) Output low voltage (IOUT = 2.0 mA) Input leakage current, any input (0 V < VIN < Vddq, all other inputs = 0 V) Output leakage current (DQ is disabled, 0 V < VOUT < VCC) Notes:
1. All voltages are referenced to VSS. 2. Vih may overshoot to Vcc + 2.0 V for pulse width of < 4ns with 3.3V. Vil may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
Symbol
Limit Values min. max. Vcc+0.3 0.8 - 0.4 5 5 2.0 - 0.3 2.4 - -5 -5
Unit Notes V V V V A A 1, 2, 3 1, 2, 3 3 3
VIH VIL VOH VOL II(L) IO(L)
Capacitance TA = 0 to 70 C; VDD = 3.3 V 0.3 V, f = 1 MHz Parameter Input capacitance (CLK) Input capacitance
(A0-A12, BA0,BA1,RAS, CAS, WE, CS, CKE, DQM, UDQM, LDQM)
Symbol
Values min. max. 4.0 5.0 2.5 2.5
Unit pF pF
CI1 CI2
Input / Output capacitance (DQ)
CIO
4.0
6.5
pF
Semiconductor Group
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HYB39S16160CT-6/-7 16MBit Synchronous DRAM
Operating Currents (TA = 0 to 70oC, VCC = 3.3V 0.3V
(Recommended Operating Conditions unless otherwise noted)
Parameter Operating Current
Symbol
Test Condition
CAS
Latency
-6 150
-7 130 mA
Note
max. max.
1, 2
Icc1
Burst Length = 4 trc>=trc (min.) tck>=tck(min.), Io = 0mA 2 bank interleave operation CKE<=VIL(max), tck>=tck(min.) tCK=infinite
Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-power down Mode Active Standby Current in Power Down Mode
Icc2P
2 1 15
2 1 15
mA mA mA CS=
High
Icc2PS CKE<=VIL(max), Icc2N
CKE>=VIH(min), tck>=tck(min.) input signals changed once in 3 cycles tCK=infinite, input signals are stable
Icc2NS CKE>=VIH(min),
5
5
mA
Icc3P
CKE<=VIL(max), tck>=tck(min.) tCK=infinite, inpit signals are stable
3 2
3 2
mA mA
Icc3PS CKE<=VIL(max),
Active Standby Current in Nonpower Down Mode Burst Operating Current Auto (CBR) Refresh Current Self Refresh Notes:
Icc3N
CKE>=VIH(min), tck>=tck(min.), changed once in 3 cycles tCK=infinite, input signals are stable
25
25
mA CS=
High, 1
Icc3NS CKE>=VIH(min),
15
15
mA
Icc4
Burst Length = full page trc = infinite tck >= tck (min.), IO = 0 mA 2 banks activated trc>=trc(min)
100
85
mA
1, 2
Icc5 Icc6
60 1
50 1
mA mA mA
1, 2
CKE=<0,2V
1, 2
1. The specified values are valid when addresses are changed no more than three times during trc(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). 2. The specified values are valid when data inputs (DQ's) are stable during tRC(min.).
Semiconductor Group
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HYB39S16160CT-6/-7 16MBit Synchronous DRAM
AC Characteristics 1)2)3) TA = 0 to 70 C; VSS = 0 V; VCC = 3.3 V 0.3 V, tT = 1 ns Parameter
Symbol
Limit Values -6
min max min
Unit
-7
max
Clock and Clock Enable
Clock Cycle Time CAS Latency = 3 tCK CAS Latency = 2 Clock Frequency CAS Latency = 3 tCK CAS Latency = 2 Access Time from Clock CAS Latency = 3 tAC CAS Latency = 2 Clock High Pulse Width Clock Low Pulse Width Transition time - - - - 2 2 0.5 166 125 5 6 - - 10 - - - - 2.5 2.5 0.5 143 115 5 6 - - 10 MHz MHz ns ns ns ns ns
2, 4
6 8
- -
7 9
- -
ns ns
tCH tCL tT
Setup and Hold Times
Input Setup Time Input Hold Time CKE Setup Time CKE Hold Time Mode Register Set-up time Power Down Mode Entry Time
tIS tIH tCKS tCKH tRSC tSB
2 1 2 1 12 0
- - - - - 6
2 1 2 1 24 0
- - - - - 7
ns ns ns ns ns ns
5 5 5 5
Common Parameters
Row to Column Delay Time Row Precharge Time Row Active Time Row Cycle Time Activate(a) to Activate(b) Command period CAS(a) to CAS(b) Command period
tRCD tRP tRAS tRC tRRD tCCD
16 16 36 54 12 1
- -
100k
18 18 42 63 14 1
- -
100k
ns ns ns ns ns CLK
- - -
- - -
Semiconductor Group
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HYB39S16160CT-6/-7 16MBit Synchronous DRAM
Parameter
Symbol
Limit Values -6
min max min
Unit
-7
max
Refresh Cycle
Refresh Period (4096 cycles) Self Refresh Exit Time
tREF tSREX
- 10
64
- 10
64
ms ns
Read Cycle
Data Out Hold Time
Data Out to Low Impedance Time Data Out to High Impedance Time DQM Data Out Disable Latency
tOH tLZ tHZ tDQZ
2 0 2 -
- - 6 2
2.5 0 2 -
- - 7 2
ns ns ns CLK
2
8
Write Cycle
Write Recovery Time DQM Write Mask Latency Write Latency
tWR tDQW tWL
6 0 0
- - -
7 0 0
- - -
ns CLK CLK
Frequency vs. AC Parameter Relationship Table: -6 -parts
CL 166 MHz 125 MHz 3 2 tRCD 3 2 tRP 3 2 tRC 9 7 tRAS 6 5 tRRD 2 2 tCCD 1 1 WL 0 0 tWR 1 1
-7 -parts:
CL 143 MHz 115 MHz 3 2 tRCD 3 2 tRP 3 2 tRC 9 7 tRAS 6 5 tRRD 2 2 tCCD 1 1 WL 0 0 tWR 1 1
Semiconductor Group
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HYB39S16160CT-6/-7 16MBit Synchronous DRAM
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet. 2. AC timing tests for LV-TTL versions have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.5 V crossover point. The transition time is measured between Vih and Vil. All AC measurements assume tT=1ns with the AC output load circuit shown in fig.1. Specified tac and toh parameters are measured with a 30 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V..
tCH 2.4 V CLOCK tCL tSETUP tHOLD 0.4 V
+ 1.5 V 50 Ohm Z=50 Ohm I/O 30 pF
tT
INPUT
1.5V
tAC tLZ tOH
tAC
I/O 30 pF
OUTPUT
1.5V
Measurement conditions for tac and toh
tHZ
fig.1
3. If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter. 4. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered.
Semiconductor Group
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HYB39S16160CT-6/-7 16MBit Synchronous DRAM
Package Outlines:
Plastic Package P-TSOPII-50 (400 mil, 0.8 mm lead pitch) Thin Small Outline Package, SMD
0.1 0.05 1 0.05 1.2 max.
0.0 0.15 +0.0 6 3
10.16 0.13
0.8 0.4 + 0.05 - 0.1 0.2
M
0.5 0.1 11.76 0.2 50x 0.1
50
26
1
20.95 0.131)
25
GPX05956
Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side
Semiconductor Group
15

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